Cadence Unveils Industry-Leading 12.8Gbps HBM4 Memory IP to Power Next-Gen AI and HPC Systems
Cadence Design Systems has released the industry's fastest High Bandwidth Memory 4 (HBM4) IP solution with a performance of 12.8Gbps, double the performance of its previous offering, HBM3E.
Designed to address the increasing data requirements of AI training and high-performance computing (HPC) systems, the Cadence HBM4 PHY and controller IP are available for customer engagement.
Cadence's HBM4 solution provides industry-leading performance with up to 12.8Gbps data rates, 60% higher than the speeds of existing HBM4 DRAM—providing sufficient system margin and forward compatibility for next-generation system-on-chip (SoC) designs.
It provides dramatic efficiency improvements, such as 20% more power efficiency per bit and 50% better area efficiency compared to its predecessor, HBM3E. Furthermore, by doubling the I/Os, the solution significantly increases overall memory bandwidth, meeting the increasing needs of AI workloads and data center operations.
Architecture and Deployment
Boyd Phelps, SVP and GM of the Silicon Solutions Group at Cadence, said, “The proliferation of generative and agentic AI applications and the resulting increase in AI workloads demand higher memory bandwidth for greater AI hardware system efficiency without further draining power.”
He added, “Cadence’s HBM4 solution addresses this insatiable need for memory bandwidth by providing the highest performance available at 12.8Gbps while maintaining area and power efficiency—key concerns for AI factories.”
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Cadence's HBM4 IP solution provides an entire memory subsystem with hardened PHY being offered on TSMC's N3 and N2 nodes and soft RTL macro for the memory controller. The design supports sophisticated features such as RAS (Reliability, Availability, and Serviceability) and BIST (Built-In Self-Test) for maximizing performance after deployment.
To speed time to market, Cadence provides a complete development and validation platform that simplifies SoC integration. This includes its LabStation software, which enables rapid post-silicon bring-up using full-featured test chips with HBM4 DRAM.
A validated reference interposer design, tested at 12.8Gbps, ensures seamless physical integration, while Cadence’s Verification IP (VIP) for HBM4 supports thorough system-level verification and features a System Performance Analyzer for optimizing performance across the memory subsystem.
