Marvell Expands AI Infrastructure with Advanced Multi-Die Packaging Solution
Marvell Technology, a leader in data infrastructure semiconductor solutions, has introduced an innovative multi-die packaging solution that enhances the efficiency and scalability of AI compute platforms.
This advanced packaging technology is part of Marvell’s broader portfolio aimed at custom AI accelerator silicon, offering a transformative approach to multi-chip designs.
Lowering Total Cost of Ownership and Improving Performance
Marvell’s new packaging solution allows for multi-chip accelerator designs that are 2.8 times larger than conventional single-die setups. By enabling more efficient die-to-die interconnect, the platform reduces power consumption, improves chiplet yields, and lowers product costs.
This new packaging method serves as a viable alternative to traditional interposer-based multi-chip solutions, providing a more cost-effective option for hyperscalers in need of high-performance AI infrastructure.
Overcoming AI Infrastructure Challenges
As AI workloads continue to expand, chip packaging has become a critical component in managing the demands of AI systems, including compute density, power efficiency, thermal dissipation, and signal integrity.
Marvell’s multi-die packaging solution addresses these needs, overcoming the challenges presented by rising supply chain complexity and long lead times. The solution provides hyperscalers with the flexibility to accelerate time-to-market while managing supply chain constraints.
Optimized for the Future of Custom AI Solutions
The multi-die packaging platform is designed with Marvell's custom HBM and CPO (chip-on-package) solutions in mind, and represents the next step in Marvell’s strategy to build the most comprehensive platform for custom AI processors (XPUs).
The new packaging solution integrates up to 1390 mm² of silicon and multiple high-bandwidth memory stacks (HBM3/3E), making it one of the largest multi-die AI accelerator solutions in the market.
Modular and Cost-Efficient Design
One of the key innovations in Marvell’s solution is the use of its re-distribution layer (RDL), which offers a more modular approach compared to traditional silicon interposers. The modular design reduces material costs and increases yield by allowing manufacturers to replace individual dies rather than entire interposers. This method also minimizes signal noise within the chiplet package, further enhancing performance and reliability.
Also read: Marvell and NVIDIA Collaborate to Offer Next-Gen AI Infrastructure with NVLink Fusion Technology
Industry Impact and Future Prospects
James Sanders, senior analyst at TechInsights, said, “Chiplets constitute one of the most dynamic segments of the semiconductor market. We anticipate that chiplet processor revenue will grow by 31% per year to reach $145 billion by 2030.”
He added, “Advanced packaging technologies are critical to the evolution of chiplets, giving designers a framework in which to experiment."
The new Marvell multi-die packaging platform is already qualified for use in current AI systems with HBM3 memory and is being developed for future HBM4 designs. The solution’s ability to integrate passive devices further enhances its capability to support complex AI workloads, positioning Marvell as a key player in the AI infrastructure market.
